gpi
Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the FPGA fabric.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sys_mgr_core | 0xFFD12000 | 0xFFD120E8 |
Size: 32
Offset: 0xE8
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
val RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
val RO 0x0 |
|||||||||||||||
gpi Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:0 | val |
The value being driven from the FPGA fabric on f2s_gp[31:0]. If the FPGA is not in User Mode, the value of this field is undefined. |
RO | 0x0 |