wddbg
Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sys_mgr_core | 0xFFD12000 | 0xFFD12008 |
Size: 32
Offset: 0x8
Access: RW
Access mode: PRIVILEGEMODE
Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
mode_3 RW 0x8 |
Reserved |
mode_2 RW 0x8 |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
mode_1 RW 0x8 |
Reserved |
mode_0 RW 0x8 |
||||||||||||
wddbg Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 27:24 | mode_3 |
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x8 | ||||||||||||||
| 19:16 | mode_2 |
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x8 | ||||||||||||||
| 11:8 | mode_1 |
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x8 | ||||||||||||||
| 3:0 | mode_0 |
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x8 |