emac0_ace

         The EMAC0 ACE-lite control register
      
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12050

Size: 32

Offset: 0x50

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

awsid

RW 0x0

Reserved

arsid

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

arsid

RW 0x0

Reserved

awdomain

RW 0x3

Reserved

ardomain

RW 0x3

emac0_ace Fields

Bit Name Description Access Reset
29:20 awsid
awsid
RW 0x0
17:8 arsid
arsid
RW 0x0
5:4 awdomain
aw domain
RW 0x3
1:0 ardomain
ar domain
RW 0x3