sdmmc_l3master 

         Controls the L3 master HPROT AHB-Lite signal.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD1202C

Size: 32

Offset: 0x2C

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

hauser22_13

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

hauser7_6

RW 0x3

Reserved

hauser0_1

RW 0x0

hprot

RW 0x1

sdmmc_l3master Fields

Bit Name Description Access Reset
25:16 hauser22_13 
bit[22:13] xsid
 RW 0x0
9:8 hauser7_6 
bit[7:6] domai
 RW 0x3
5:4 hauser0_1 
bit[1] secure bit[0] allocate
 RW 0x0
3:0 hprot 
HPROT[3] Cachable
  0: L3 master accesses for the module are non-cacheable.
  1: L3 master accesses for the module are cacheable.
==========================
HPROT[2] Bufferable
  0: L3 master accesses for the module are not bufferable.
  1: L3 master accesses for the module are bufferable.
==========================
HPROT[1] Privileged
  0: L3 master accesses for the module are not privileged.
  1: L3 master accesses for the module are privileged.
==========================
HPROT[0] Data/Opcode
  0: Specifies if the L3 master access is for opcode
  1: Specifies if the L3 master access is for data
 RW 0x1