etr_l3master

         Register for ACE-lite control - etr_l3master
      
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12078

Size: 32

Offset: 0x78

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

aruser

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ardomain

RW 0x3

awdomain

RW 0x3

Reserved

awuser

RW 0x0

etr_l3master Fields

Bit Name Description Access Reset
25:16 aruser
ar sid register
RW 0x0
15:14 ardomain
ar domain regisger
RW 0x3
13:12 awdomain
aw domain register
RW 0x3
9:0 awuser
aw sid register
RW 0x0