fpgaintf_en_2 

         Used to disable individual interfaces between the FPGA and HPS.
This register is reset only on a cold reset (ignores warm reset).
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD1206C

Size: 32

Offset: 0x6C

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

spim_1

RW 0x0

Reserved

spim_0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sdmmc

RW 0x0

Reserved

nand

RW 0x0

Reserved

fpgaintf_en_2 Fields

Bit Name Description Access Reset
24 spim_1 
Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation.
The array index corresponds to the SPI master module instance.
Value Description
0 Disable
1 Enable
RW 0x0
16 spim_0 
Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation.
The array index corresponds to the SPI master module instance.
Value Description
0 Disable
1 Enable
RW 0x0
8 sdmmc 
Used to disable signals from the FPGA fabric to the SD/MMC controller module that could potentially interfere with its normal operation.
Value Description
0 Disable
1 Enable
RW 0x0
4 nand 
Used to disable signals from the FPGA fabric to the NAND flash controller module that could potentially interfere with its normal operation.
Value Description
0 Disable
1 Enable
RW 0x0