iocsrclk_gate

         IO Clock control

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD120E0`

Size: 32

Offset: 0xE0

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`tilec` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`tileb` `RW 0x0`	`Reserved`							`tilea` `RW 0x0`

iocsrclk_gate Fields

Bit	Name	Description	Access	Reset
16	`tilec`	Tile C clock control	`RW`	`0x0`
8	`tileb`	Tile B clock control	`RW`	`0x0`
0	`tilea`	Tile A clock control	`RW`	`0x0`