rbr_thr_dll |
0x0 |
32 |
RW |
0x0 |
Rx Buffer, Tx Holding, and Divisor Latch Low |
ier_dlh |
0x4 |
32 |
RW |
0x0 |
Interrupt Enable and Divisor Latch High |
iir |
0x8 |
32 |
RO |
0x1 |
Interrupt Identity Register (when read) |
fcr |
0x8 |
32 |
WO |
0x0 |
FIFO Control (when written) |
lcr |
0xC |
32 |
RW |
0x0 |
Line Control Register (When Written) |
mcr |
0x10 |
32 |
RW |
0x0 |
Modem Control Register |
lsr |
0x14 |
32 |
RO |
0x60 |
Line Status Register |
msr |
0x18 |
32 |
RO |
0x0 |
Modem Status Register |
scr |
0x1C |
32 |
RW |
0x0 |
Scratchpad Register |
srbr |
0x30 |
32 |
RW |
0x0 |
Shadow Receive Buffer Register |
sthr |
0x34 |
32 |
RW |
0x0 |
Shadow Transmit Buffer Register |
far |
0x70 |
32 |
RW |
0x0 |
FIFO Access Register |
tfr |
0x74 |
32 |
RO |
0x0 |
Transmit FIFO Read Register |
RFW |
0x78 |
32 |
WO |
0x0 |
Receive FIFO Write |
usr |
0x7C |
32 |
RO |
0x6 |
UART Status Register |
tfl |
0x80 |
32 |
RO |
0x0 |
Transmit FIFO Level |
rfl |
0x84 |
32 |
RO |
0x0 |
Receive FIFO Level Write |
srr |
0x88 |
32 |
WO |
0x0 |
Software Reset Register |
srts |
0x8C |
32 |
RW |
0x0 |
Shadow Request to Send |
sbcr |
0x90 |
32 |
RW |
0x0 |
Shadow Break Control Register |
sdmam |
0x94 |
32 |
RW |
0x0 |
Shadow DMA Mode |
sfe |
0x98 |
32 |
RW |
0x0 |
Shadow FIFO Enable |
srt |
0x9C |
32 |
RW |
0x0 |
Shadow Rx Trigger |
stet |
0xA0 |
32 |
RW |
0x0 |
Shadow Tx Empty Trigger |
htx |
0xA4 |
32 |
RW |
0x0 |
Halt Tx |
dmasa |
0xA8 |
32 |
WO |
0x0 |
DMA Software Acknowledge |
cpr |
0xF4 |
32 |
RO |
0x373F32 |
Component Parameter Register |
ucv |
0xF8 |
32 |
RO |
0x3331312A |
Component Version |
ctr |
0xFC |
32 |
RO |
0x44570110 |
Component Type Register |