stet
This is a shadow register for the Tx empty trigger bits (FCR[5:4]).
| Module Instance | Base Address | Register Address |
|---|---|---|
| uart0 | 0xFFC02000 | 0xFFC020A0 |
| uart1 | 0xFFC03000 | 0xFFC030A0 |
Offset: 0xA0
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
stet RW 0x0 |
||||||||||||||
stet Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1:0 | stet | This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the Tx empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. These threshold levels are also described in. The enum trigger levels are supported.
|
RW | 0x0 |