srbr

Used to accomadate burst accesses from the master.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC02030`
`uart1`	`0xFFC03000`	`0xFFC03030`

Offset: 0x30

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`srbr` `RW 0x0`

srbr Fields

Bit	Name	Description	Access	Reset
7:0	`srbr`	This is a shadow register for the RBR and has been allocated one 32-bit location so as to accommodate burst accesses from the master.This register contains the data byte received on the serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled, bit [0] of register FCR set to zero, the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur.	`RW`	`0x0`