ier_dlh

This is a multi-function register. This register enables/disables receive and transmit interrupts and also controls the most-significant 8-bits of the baud rate divisor. Divisor Latch High Register: This register is accessed when the DLAB bit [7] of the LCR Register is set to 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor): Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 l4_sp_clk clock cycles should be allowed to pass before transmitting or receiving data. Interrupt Enable Register: This register may only be accessed when the DLAB bit [7] of the LCR Register is set to 0.Allows control of the Interrupt Enables for transmit and receive functions.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02004
uart1 0xFFC03000 0xFFC03004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ptime_dlh7

RW 0x0

dlh6

RW 0x0

dlh5

RW 0x0

dlh4

RW 0x0

edssi_dhl3

RW 0x0

elsi_dhl2

RW 0x0

etbei_dlhl

RW 0x0

erbfi_dlh0

RW 0x0

ier_dlh Fields

Bit Name Description Access Reset
7 ptime_dlh7

Divisor Latch High Register: Bit 7 of DLH value. Interrupt Enable Register: This is used to enable/disable the generation of THRE Interrupt.

Value Description
0x0 disable tx-hold-reg-empty interrupt
0x1 enable tx-hold-reg-empty interrupt
RW 0x0
6 dlh6

Bit 6 of DLH value.

 RW 0x0
5 dlh5

Bit 5 of DLH value.

 RW 0x0
4 dlh4

Bit 4 of DLH value.

 RW 0x0
3 edssi_dhl3

Divisor Latch High Register: Bit 3 of DLH value. Interrupt Enable Register: This is used to enable/disable the generation of Modem Status Interrupts. This is the fourth highest priority interrupt.

Value Description
0x0 disable modem status interrupt
0x1 enable modem status interrupt
RW 0x0
2 elsi_dhl2

Divisor Latch High Register: Bit 2 of DLH value. Interrupt Enable Register: This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt.

Value Description
0x0 Disable interrupt line stat
0x1 Enable interrupt line stat
RW 0x0
1 etbei_dlhl

Divisor Latch High Register: Bit 1 of DLH value. Interrupt Enable Register: Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.

Value Description
0x0 Tx disable
0x1 Tx enable
RW 0x0
0 erbfi_dlh0

Divisor Latch High Register: Bit 0 of DLH value. Interrupt Enable Register: Used to enable/disable the generation of the Receive Data Available Interrupt and the Character Timeout Interrupt(if FIFO's enabled). These are the second highest priority interrupts.

Value Description
0x0 Interrupt Disable
0x1 Interrupt Enable
RW 0x0