RFW

Used only with FIFO access test mode.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC02078`
`uart1`	`0xFFC03000`	`0xFFC03078`

Offset: 0x78

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`RFFE` `WO 0x0`	`rfpe` `WO 0x0`	`rfwd` `WO 0x0`

RFW Fields

Bit	Name	Description	Access	Reset
9	`RFFE`	These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFO's are not enabled, this bit is used to write framing error detection information to the RBR.	`WO`	`0x0`
8	`rfpe`	These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFO's are not enabled, this bit is used to write parity error detection information to the RBR.	`WO`	`0x0`
7:0	`rfwd`	These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFO's are not enabled, the data that is written to the RFWD is pushed into the RBR.	`WO`	`0x0`