fcr

This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the uart_rts_n signal will be de-asserted. It also determines when the uart_dma_rx_req_n signal will be asserted when in certain modes of operation.

This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the uart DMA transmit request signal uart_dma_tx_req_n will be asserted when in certain modes of operation.

This determines the DMA signalling mode used for the uart_dma_tx_req_n and uart_dma_rx_req_n output signals when additional DMA handshaking signals are not selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, the uart_dma_tx_req_n signal goes active low under the following conditions: -When the Transmitter Holding Register is empty in non-FIFO mode. -When the transmitter FIFO is empty in FIFO mode with Programmable THRE interrupt mode disabled. -When the transmitter FIFO is at or below the programmed threshold with Programmable THRE interrupt mode enabled. It goes inactive under the following conditions -When a single character has been written into the Transmitter Holding Register or transmitter FIFO with Programmable THRE interrupt mode disabled. -When the transmitter FIFO is above the threshold with Programmable THRE interrupt mode enabled. DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made continuously until the receiver FIFO has been emptied or the transmit FIFO has been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the following conditions: -When the transmitter FIFO is empty with Programmable THRE interrupt mode disabled. -When the transmitter FIFO is at or below the programmed threshold with Programmable THRE interrupt mode enabled.

Resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA Tx request and single signals when additional DMA handshaking is used. Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

Resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA Rxrequest and single signals. Note that this bit is self-clearing' and it is not necessary to clear this bit.

Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value of this bit is changed both the Tx and Rx controller portion of FIFO's will be reset.