usr

Status of FIFO Operations.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC0207C`
`uart1`	`0xFFC03000`	`0xFFC0307C`

Offset: 0x7C

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`											`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`Reserved`

usr Fields

Bit

Name

Description

Access

Reset

rff

This Bit is used to indicate that the receive FIFO is completely full. This bit is cleared when the Rx FIFO is no longer full.

Value	Description
0x0	Receiive FIFO not full
0x1	Transmit FIFO is full

RO

0x0

rfne

This Bit is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the Rx FIFO is empty.

Value	Description
0x0	Receiive FIFO is empty
0x1	Receive FIFO is not empty

RO

0x0

tfe

This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the Tx FIFO is no longer empty.

Value	Description
0x0	Transmit FIFO is not empty
0x1	Transmit FIFO is empty

RO

0x1

tfnf

This Bit is used to indicate that the transmit FIFO in not full. This bit is cleared when the Tx FIFO is full.

Value	Description
0x0	Transmit FIFO is full
0x1	Transmit FIFO is not full

RO

0x1