cpr

Describes various fixed hardware setups states.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC020F4
uart1 0xFFC03000 0xFFC030F4

Offset: 0xF4

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

fifo_mode

RO 0x37
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dma_extra

RO 0x1

uart_add_encoded_param

RO 0x1

shadow

RO 0x1

fifo_stat

RO 0x1

fifo_access

RO 0x1

additional_feat

RO 0x1

sir_lp_mode

RO 0x0

sir_mode

RO 0x0

thre_mode

RO 0x1

afce_mode

RO 0x1

Reserved

apbdatawidth

RO 0x2

cpr Fields

Bit Name Description Access Reset
23:16 fifo_mode

Receiver and Transmitter FIFO depth in bytes.

Value Description
0x80 FIFO Depth 128 bytes
RO 0x37
13 dma_extra

Configures the peripheral to have four additional DMA signals on the interface.

Value Description
0x1 DMA Extra Supported
RO 0x1
12 uart_add_encoded_param

Configures the peripheral to have a configuration identification register.

Value Description
0x1 ID register present
RO 0x1
11 shadow

Configures the peripheral to have seven additional registers that shadow some of the existing register bits that are regularly modified by software. These can be used to reduce the software overhead that is introduced by having to perform read-modify writes.

Value Description
0x1 Shadow Supported
RO 0x1
10 fifo_stat

Configures the peripheral to have three additional FIFO status registers.

Value Description
0x1 FIFO Stat Supported
RO 0x1
9 fifo_access

Configures the peripheral to have a programmable FIFO access mode. This is used for test purposes, to allow the receiver FIFO to be written and the transmit FIFO to be read when FIFOs are implemented and enabled.

Value Description
0x1 FIFO Access Supported
RO 0x1
8 additional_feat

Configures the uart to include fifo status register, shadow registers and encoded parameter register.

Value Description
0x1 Additional Features Supported
RO 0x1
7 sir_lp_mode

LP Sir Mode not used in this application.

Value Description
0x0 LP Sir Mode Not Supported
RO 0x0
6 sir_mode

Sir mode not used in this application.

Value Description
0x0 Sir Mode Not Supported
RO 0x0
5 thre_mode

Programmable Transmitter Hold Register Empty interrupt

Value Description
0x1 Programmable Tx Hold Reg. Empty interrupt present
RO 0x1
4 afce_mode

Allows auto flow control.

Value Description
0x1 Auto Flow
RO 0x1
1:0 apbdatawidth

Fixed to support an ABP data bus width of 32-bits.

Value Description
0x2 APB Data Width = 32-bits
RO 0x2