msr

It should be noted that whenever bits 0, 1, 2 or 3 are set to logic one, to indicate a change on the modem control inputs, a modem status interrupt will be generated if enabled via the IER regardless of when the change occurred. Since the delta bits (bits 0, 1, 3) can get set after a reset if their respective modem signals are active (see individual bits for details), a read of the MSR after reset can be performed to prevent unwanted interrupts.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC02018`
`uart1`	`0xFFC03000`	`0xFFC03018`

Offset: 0x18

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`dcd` `RO 0x0`	`ri` `RO 0x0`	`dsr` `RO 0x0`	`cts` `RO 0x0`	`ddcd` `RO 0x0`	`teri` `RO 0x0`	`ddsr` `RO 0x0`	`dcts` `RO 0x0`

msr Fields

Bit

Name

Description

Access

Reset

dcd

This is used to indicate the current state of the modem control line uart_dcd_n. That is this bit is the complement uart_dcd_n. When the Data Carrier Detect input (uart_dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (uart_out2).

Value	Description
0x0	uart_dcd_n input is de-asserted (logic 1)
0x1	uart_dcd_n input is asserted (logic 0)

RO

0x0

ri

This bit is used to indicate the current state of the modem control line uart_ri_n. That is this bit is the complement uart_ri_n. When the Ring Indicator input (uart_ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. In Loopback Mode bit [4] of register MCR set to one, RI is the same as bit [2] uart_out1_n of register MCR.

Value	Description
0x0	uart_ri_n input is de-asserted (logic 1)
0x1	uart_ri_n input is asserted (logic 0)

RO

0x0

dsr

This is used to indicate the current state of the modem control line uart_dsr_n. That is this bit is the complement f uart_dsr_n. When the Data Set Ready input (uart_dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the uart. In Loopback Mode bit [4] of register MCR is set to one, DSR is the same as bit [0] (DTR) of register MCR.

Value	Description
0x0	uart_dsr_n input is de-asserted (logic 1)
0x1	uart_dsr_n input is asserted (logic 0)

RO

0x0

cts

This is used to indicate the current state of the modem control line uart_cts_n. That is, this bit is the complement uart_cts_n. When the Clear to Send input (uart_cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the uart. In Loopback Mode bit [4] of register MCR is set to one, CTS is the same as bit [1] RTS of register MCR.

Value	Description
0x0	uart_cts_n input is de-asserted (logic 1)
0x1	uart_cts_n input is asserted (logic 0)

RO

0x0

ddcd

This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback Mode bit [4] of register MCR is set to one, DDCD reflects changes bit [3] uart_out2 of register MCR. Note: If the DDCD bit is not set and the uart_dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit will get set when the reset is removed if the uart_dcd_n signal remains asserted.

Value	Description
0x0	no change on uart_dcd_n since last read of MSR
0x1	change on uart_dcd_n since last read of MSR

RO

0x0

teri

This is used to indicate that a change on the input uart_ri_n (from an active low, to an inactive high state) has occurred since the last time the MSR was read. Reading the MSR clears the TERI bit. In Loopback Mode bit [4] of register MCR is set to one, TERI reflects when bit [2] of register MCR has changed state from a high to a low.

Value	Description
0x0	no change on uart_ri_n since last read of MSR
0x1	change on uart_ri_n since last read of MSR

RO

0x0

ddsr

This is used to indicate that the modem control line uart_dsr_n has changed since the last time the MSR was read. Reading the MSR clears the DDSR bit.In Loopback Mode (MCR[4] set to one), DDSR reflects changes on bit [0] DTR of register MCR . Note, if the DDSR bit is not set and the uart_dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit will get set when the reset is removed if the uart_dsr_n signal remains asserted.

Value	Description
0x0	no change on uart_dsr_n since last read of MSR
0x1	change on uart_dsr_n since last read of MSR

RO

0x0

dcts

This is used to indicate that the modem control line uart_cts_n has changed since the last time the MSR was read. That is: Reading the MSR clears the DCTS bit. In Loopback Mode bit [4] of MCR set to one, DCTS reflects changes on bit [1] RTS of register MCR. Note: If the DCTS bit is not set and the uart_cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit will get set when the reset is removed if the uart_cts_n signal remains asserted.

Value	Description
0x0	no change on uart_cts_n since last read of MSR
0x1	change on uart_cts_n since last read of MSR

RO

0x0