UART Module Summary

Registers in the UART module

Module Instance	Base Address
`uart0`	`0xFFC02000`
`uart1`	`0xFFC03000`

Register Address Offset	Bit Fields
`rbr_thr_dll` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`value` `RW 0x0`
`ier_dlh` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`ptime_dlh7` `RW 0x0`	`dlh6` `RW 0x0`	`dlh5` `RW 0x0`	`dlh4` `RW 0x0`	`edssi_dhl3` `RW 0x0`	`elsi_dhl2` `RW 0x0`	`etbei_dlhl` `RW 0x0`	`erbfi_dlh0` `RW 0x0`
`iir` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`fifoen` `RO 0x0`		`Reserved`		`id` `RO 0x1`
`fcr` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rt` `WO 0x0`		`tet` `WO 0x0`		`dmam` `WO 0x0`	`xfifor` `WO 0x0`	`rfifor` `WO 0x0`	`fifoe` `WO 0x0`
`lcr` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`dlab` `RW 0x0`	`break` `RW 0x0`	`Reserved`	`eps` `RW 0x0`	`pen` `RW 0x0`	`stop` `RW 0x0`	`dls` `RW 0x0`
`mcr` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`afce` `RW 0x0`	`loopback` `RW 0x0`	`out2` `RW 0x0`	`out1` `RW 0x0`	`rts` `RW 0x0`	`dtr` `RW 0x0`
`lsr` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rfe` `RO 0x0`	`temt` `RO 0x1`	`thre` `RO 0x1`	`bi` `RO 0x0`	`fe` `RO 0x0`	`pe` `RO 0x0`	`oe` `RO 0x0`	`dr` `RO 0x0`
`msr` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`dcd` `RO 0x0`	`ri` `RO 0x0`	`dsr` `RO 0x0`	`cts` `RO 0x0`	`ddcd` `RO 0x0`	`teri` `RO 0x0`	`ddsr` `RO 0x0`	`dcts` `RO 0x0`
`scr` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`scr` `RW 0x0`
`srbr` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`srbr` `RW 0x0`
`sthr` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`sthr` `RW 0x0`
`far` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`srbr_sthr` `RW 0x0`
`tfr` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`tfr` `RO 0x0`
`RFW` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`RFFE` `WO 0x0`	`rfpe` `WO 0x0`	`rfwd` `WO 0x0`
`usr` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`Reserved`
`tfl` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`tfl` `RO 0x0`
`rfl` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rfl` `RO 0x0`
`srr` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`xfr` `WO 0x0`	`rfr` `WO 0x0`	`ur` `WO 0x0`
`srts` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`srts` `RW 0x0`
`sbcr` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sbcr` `RW 0x0`
`sdmam` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sdmam` `RW 0x0`
`sfe` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sfe` `RW 0x0`
`srt` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`srt` `RW 0x0`
`stet` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`stet` `RW 0x0`
`htx` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`htx` `RW 0x0`
`dmasa` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`dmasa` `WO 0x0`
`cpr` `0xF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`								`fifo_mode` `RO 0x37`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`dma_extra` `RO 0x1`	`uart_add_encoded_param` `RO 0x1`	`shadow` `RO 0x1`	`fifo_stat` `RO 0x1`	`fifo_access` `RO 0x1`	`additional_feat` `RO 0x1`	`sir_lp_mode` `RO 0x0`	`sir_mode` `RO 0x0`	`thre_mode` `RO 0x1`	`afce_mode` `RO 0x1`	`Reserved`		`apbdatawidth` `RO 0x2`
`ucv` `0xF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`uart_component_version` `RO 0x3331312A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`uart_component_version` `RO 0x3331312A`
`ctr` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`peripheral_id` `RO 0x44570110`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`peripheral_id` `RO 0x44570110`