Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Adding the PMON FPGA IP to Your Design in Platform Designer 7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Adding the PMON FPGA IP to Your Design in Platform Designer
7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions

The following table summarizes the PMON IP parameters.

Table 2.  PMON IP Parameters
Parameter Range Description
Remote access via JTAG True, False Choose whether to have access to Control and Status Registers (CSRs) via JTAG or through the AXI-Lite interface. The default value is False.
Unit Monitor 0
Unit ID 0-65335 Set to differentiate instances of PMON in hardware and simulation via the Unit ID CSR value. The default value is 0.
AXI Interface
Write ID Width 1-18 Specifies widths of AWID and BID ports of the AXI4 bus. The default value is 7.
Write Address Width 4-64 Specifies width of AWADDR port of the AXI4 bus. The default value is 31.
Note: The minimum valid value equals floor(log2(N))+ 1 where N is the input value for the Write Data Width parameter.
Use AWLOCK True, False Enables AWLOCK port of the AXI4 bus. The default value is True.
Use AWCACHE True, False Enables AWCACHE port of the AXI4 bus. The default value is True.
Use AWQOS True, False Enables AWQOS port of the AXI4 bus. The default value is True.
Use AWREGION True, False Enables AWREGION port of the AXI4 bus. The default value is False.
Use AWUSER True, False Enables AWUSER port of the AXI4 bus. The default value is True.
AWUSER Width 1-64 Specifies width of AWUSER port of the AXI4 bus. The default value is 8.
Read ID Width 1-18

Specifies widths of ARID and RID ports of the AXI4 bus. The default value is 7.
Read Address Width 1-64 Specifies width of ARADDR port of the AXI4 bus. The default value is 31.
Use ARLOCK True, False Enables ARLOCK port of the AXI4 bus. The default value is True.
Use ARCACHE True, False Enables ARCACHE port of the AXI4 bus. The default value is True.
Use ARQOS True, False Enables ARQOS port of the AXI4 bus. The default value is True.
Use ARREGION True, False Enables ARREGION port of the AXI4 bus. The default value is False.
Use ARUSER True, False Enables ARUSER port of the AXI4 bus. The default value is True.
ARUSER Width 1-64 Enables ARUSER port of the AXI4 bus. Specifies width of ARUSER port of the AXI4 bus. The default value is 8.
Write Data Width 8-192, 256-320, 512-576, 1024-1088 Specifies width of write data. 2^N bits are mapped to the WDATA port and the remainder of the bits up to a maximum of 64 are mapped to the WUSER port. N is a integer ranging from 3 to 10.
Read Data Width 8-192, 256-320, 512-576, 1024-1088 Specifies width of read data. 2^N bits are mapped to the RDATA port and the remainder of the bits up to a maximum of 64 are mapped to the RUSER port. N is a integer ranging from 3 to 10.
Use BUSER True, False Enables BUSER port of the AXI4 bus. The default value is False.
BUSER Width 1-64 Specifies width of BUSER port of the AXI4 bus. The default value is 8.
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