Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817760
Date 7/08/2024
Public
Document Table of Contents

A.1. Derived Parameters from PMON IP

This topic describes the set of parameters that you can use to calculate the AXI4 bandwidth for read or write channels.

The following parameters can be derived through a combination of two or more counters set to specific AXI4 events. The formula uses the following AXI4 parameters:

  • AR - Read address channel
  • R - Read data channel
  • AW - Write address channel
  • W - Write data channel
  • B - Write response channel
  • Total traffic duration - Number of cycles from first AR | AW | W to last transaction on R | B channel.

Equations

Average number of data transactions per cycle =

Read efficiency =

Write efficiency =

Average Read latency =

Average Write latency =

You can also measure these AXI4 sub-channel efficiencies using the following equations:

Read address channel efficiency =

Read data channel efficiency =

Write command channel efficiency =

Write data channel efficiency =

Write response channel efficiency =