Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Adding the PMON FPGA IP to Your Design in Platform Designer 7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Adding the PMON FPGA IP to Your Design in Platform Designer
7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 1.1.0
  • In the Performance Monitor IP Functional Description chapter:
    • Updated the PMON Implementation Block Diagram figure.
    • In the AXI4 Traffic Limitations topic, modified the third bullet point.
  • In the Performance Monitor FPGA IP Interface Signals chapter:
    • Modified the description of the sink_axi4_rvalid and sink_axi4_rid ports in the Sink Read Data Channel Signals table.
    • Modified the description of the src_axi4_rid port in the Source Read Data Channel Signals table.
    • In the Registers section:
      • Added a table explaining the attribute abbreviations in use in the various Registers tables.
      • Streamlined the heading structures in the various Registers tables.
      • Corrected the attribute indicators for some fields in the Global Discovery, Unit Discovery, Unit Control, Counter Control, and Data register tables.
  • Added the Adding the PMON FPGA IP to Your Design in Platform Designer chapter.
  • In the PMON Library Functions appendix:
    • Modified step 3 of the procedure.
    • Modified the Tip preceding the PMON Library Functions table.
    • Added a row to the PMON Configuration Table.
    • Made minor editorial improvements to the Derived Parameters from PMON IP topic.
2024.04.01 24.1 1.0.0 Initial release.
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