Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Adding the PMON FPGA IP to Your Design in Platform Designer 7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Adding the PMON FPGA IP to Your Design in Platform Designer
7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

6. Adding the PMON FPGA IP to Your Design in Platform Designer

Follow this procedure to connect an instance of the PMON IP to AXI4 IPs in your design in Platform Designer.
  1. To enable the PMON FPGA IP for use in Platform Designer, instantiate the following:
    • PMON FPGA IP
    • AXI4 manager IP
    • AXI4 subordinate IP
    • Clock and reset IPs
    Note: This example uses the Test Engine IP as AXI4 manager and NoC Initiator IP as AXI4 subordinate. These IPs are used as substitutes for the AXI4 manager/subordinate IPs. In general, you can use the PMON IP with any AXI4 IP.
  2. Make the appropriate connections, as follows:
    1. Connect the src_axi4 (AXI4 manager) port to the AXI4 subordinate.
    2. Connect sink_axi4 (AXI4 subordinate) port to the AXI4 manager.
    3. Connect the csr_clk/csr_reset_n ports to the appropriate PLL and reset IPs.
    4. Connect the clk and reset_n port of the PMON IP to match the AXI4 interface being monitored.
  3. After you make the necessary connections in the Platform Designer, ensure that you specify the correct width of the AXI4 parameters from the PMON IP to match the AXI4 IPs.
  4. Generate HDL for your design.
Figure 3. Connections in Platform Designer
Level Two Title