Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817760
Date 7/08/2024
Public
Document Table of Contents

5.3. AXI4-Lite Interface Signals

This interface is optional and is not available if you set the Remote JTAG parameter to True.

Table 14.  Sink AXI4-Lite Signals
Port Name Width Direction Description
sink_axi4lite_awaddr 20 Input Write Address.
sink_axi4lite_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
sink_axi4lite_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
sink_axi4lite_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
sink_axi4lite_wdata 32 Input Write Data.
sink_axi4lite_wstrb 4 Input Write Strobes (Byte Enables).
sink_axi4lite_wvalid 1 Input Write Channel Valid. This signal indicates that valid write data and strobes are available.
sink_axi4lite_wready 1 Output Write Channel Ready. This signal indicates that the subordinate can accept the write data.
sink_axi4lite_bresp 2 Output Write Response. This signal indicates the result of the Write command.
sink_axi4lite_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
sink_axi4lite_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
sink_axi4lite_araddr 20 Input Read address.
sink_axi4lite_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
sink_axi4lite_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
sink_axi4lite_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
sink_axi4lite_rdata 32 Output Read data.
sink_axi4lite_rresp 2 Output Read response. This signal indicates the status of the read transfer.
sink_axi4lite_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available.
sink_axi4lite_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.