Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817760
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Adding the PMON FPGA IP to Your Design in Platform Designer 7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Adding the PMON FPGA IP to Your Design in Platform Designer
7. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

5.3. AXI4-Lite Interface Signals

This interface is optional and is not available if you set the Remote JTAG parameter to True.

Table 14.  Sink AXI4-Lite Signals
Port Name Width Direction Description
sink_axi4lite_awaddr 20 Input Write Address.
sink_axi4lite_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
sink_axi4lite_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
sink_axi4lite_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
sink_axi4lite_wdata 32 Input Write Data.
sink_axi4lite_wstrb 4 Input Write Strobes (Byte Enables).
sink_axi4lite_wvalid 1 Input Write Channel Valid. This signal indicates that valid write data and strobes are available.
sink_axi4lite_wready 1 Output Write Channel Ready. This signal indicates that the subordinate can accept the write data.
sink_axi4lite_bresp 2 Output Write Response. This signal indicates the result of the Write command.
sink_axi4lite_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
sink_axi4lite_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
sink_axi4lite_araddr 20 Input Read address.
sink_axi4lite_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
sink_axi4lite_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
sink_axi4lite_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
sink_axi4lite_rdata 32 Output Read data.
sink_axi4lite_rresp 2 Output Read response. This signal indicates the status of the read transfer.
sink_axi4lite_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available.
sink_axi4lite_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.

Level Two Title