Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817760
Date 7/08/2024
Public
Document Table of Contents

3.1. AXI4 Traffic Limitations

The AXI4 interface has the following limitations for collecting performance metrics.
  • Not all metrics can be provided in a single run of the application.
  • Supports a maximum of 65,533 outstanding transactions for accurate latency metrics.
  • Does not support maximum or minimum latency. If the maximum filter is applied to the total read/write latency event, the counter returns the maximum number of outstanding read/write transactions, rather than the maximum latency.
  • Requires no traffic gaps on read or write channels greater than 65,535 cycles to measure efficiency accurately.
  • Requires at least 2 transactions on an AXI4 subchannel to measure efficiency for the subchannel.
  • Counters are 48 bits; variable sizes are not currently supported.
  • Does not support metric configuration mid traffic.
  • Reading metrics mid traffic provides an approximation rather than an exact value.
  • Supports a maximum of 64 monitors in the system.
  • Requires symmetry in RDATA and WDATA widths as well as ARID and AWID widths.