Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817760
Date 7/08/2024
Public
Document Table of Contents

5.1. Clock and Reset Signals

Table 3.  Clock and Reset Signals
Port Name Direction Description
clk Input Core clk matching that of the AXI4 interface on which PMON is collecting metrics.
csr_clk Input Clock for the CSR space which can be accessed by the AXI-lite interface.
reset_n Input Reset tied to the AXI4 interface on which PMON is collecting metrics.
csr_reset_n Input Reset for the CSR space which can be accessed by the AXI-lite interface. Resets Counter control, data and status registers of PMON but not internal state.