Visible to Intel only — GUID: vmv1673393438502
Ixiasoft
Visible to Intel only — GUID: vmv1673393438502
Ixiasoft
5.1.6.1.1. Transmit and Receive Data FIFO Buffers
The transmit FIFO (TX FIFO) buffers the data transferred from the application to the XGMAC. Similarly, the receive FIFO (RX FIFO) stores the Ethernet packets received from the line until they can be transferred to the application. Both TX/RX FIFOs are based on ASYNC 2-Port RAM (DPRAM) and utilize the same memory interfaces connected to XGMAC core.
The TX FIFO buffer is a 32 KB dual ported memory whereas RX FIFO buffer is 16 KB dual ported memory. Width of data bus is 68 bits. The additional 4 bits (64 bits + 4 additional bits) are used for storing the control information (byte enable, SOP, EOP and etc.)
- A data packet size of 16K x 1B queue is physically stored as a 2K x 8B queue for RX FIFO
- A data packet size of 32K x 1B queue is physically stored as a 4K x 8B queue for TX FIFO
- Port A is used to write the frame data
- Port B is used to read the frame data
- Both write and read consist of different clock domains
For TX FIFO use case:
- TX FIFO write interface is synchronous to the application clock (aclk_i)
- TX FIFO read interface is synchronous to the EMAC transmit clock (clk_tx_312pt5_i)
- RX FIFO read interface is synchronous to the application clock (aclk_i)
- RX FIFO write interface is synchronous to the EMAC receive clock (clk_rx_312pt5_i)