Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: iij1719871544201
Ixiasoft
Visible to Intel only — GUID: iij1719871544201
Ixiasoft
13.4.4.6. Programming QoS Limiter Mode
QoS bandwidth limiter mode is mode 1. To put the QoS generator in limiter mode, set the registers as shown in the following table.
Register | Field | Value |
---|---|---|
I_main_QosGenerator_Mode | MODE | 1 |
I_main_QosGenerator_Priority | P0 | Urgency for write transactions |
I_main_QosGenerator_Priority | P1 | Urgency for read transactions |
I_main_QosGenerator_Bandwidth | BANDWIDTH | Maximum bandwidth. Value = (bandwidth / frequency) * 256 |
I_main_QosGenerator_Saturation | SATURATION | Measurement window for bandwidth, in units of bytes/16. This register specifies the maximum number of bytes that the initiator can transmit or receive at full speed before the limiter triggers. |
Higher priority (urgency) values mean that a packet receives preferential treatment at each arbitration node. For detailed information about setting bandwidth and saturation, refer to Bandwidth and Saturation. When you switch QoS modes, the bandwidth counter is reset.