Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 11/27/2024
Public
Document Table of Contents

2.3.4.1.8. PHY Interface

Different external PHY interfaces are provided depending on whether the Ethernet controller signals are routed through the HPS I/O pins or the FPGA I/O pins.

The PHY interface supported using the HPS I/O pins is:

  • Reduced Gigabit Media Independent Interface (RGMII)

The PHY interfaces support using the FPGA I/O pins are:

  • Reduced Gigabit Media Independent Interface (RGMII) with additional required adapter logic
  • Serial Gigabit Media Independent Interface (SGMII) with additional required adapter logic supported through True Differential Signaling (TDS) I/O
  • Serial Gigabit Media Independent Interface+ (SGMII+) with additional required adapter logic supported through serial transceiver interface with FPGA I/O
Note: The EMAC interface presented to the FPGA fabric is the Gigabit Media Independent Interface (GMII). You can use the signals of this interface to enable RGMII, SGMII and SGMII+ through additional soft logic adaptation.
The Ethernet Controller has two options for the management control interface used for configuration and status monitoring of the PHY:
  • Management Data Input/Output (MDIO)
  • I2C PHY management through a separate I2C module within the HPS