Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 11/27/2024
Public
Document Table of Contents

14.6.3.4.1.2. Double-Bit Error Test

This sequence tests the double-bit error detection in the ECC decoder.
  1. Enable the ECC by setting the ECC_EN bit in the CTRL register.
  2. Set the Data override (DATAOVR) bit in the ECC_accctrl register.
  3. Write data to an address location in memory using a normal memory write. The correct ECC data should be generated.
  4. Write a data value that has two bits altered in the ECC_WData3bus through ECC_WData0bus registers and write the address of the memory location in the ECC_Addrbus.
  5. Configure the ECC_accctrl register to a write and set the ENBUSA bit of the ECC_startacc register to initiate the write. If the memory is dual-ported, an ENBUSB bit could optionally be enabled depending on the port access.
  6. Read the same memory location using a normal memory read access. Expect a double-bit error to be logged without data correction. Refer to the Error Logging section for more details about identifying errors.