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Visible to Intel only — GUID: cru1684440120014
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5.3.6.5.4. Scrambling Support
The NAND Flash controller supports data scrambling/de-scrambling of data read/written from/to the Flash device. This may help to remove repetitive patterns writing in flash, reducing the chances of data corruption in a page. The scrambling is achieved by pseudo random bit sequence generated by 2 32-bit scrambler initialized with different seeds (0xAAAAFFFF and 0x55556666) using the polynomial:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
For every 64-bit of data word the scramblers together generate a word of same size. During write operations, bit-wise XOR operation is applied to data after BCH has generated the ECC check bits. In read operations, bit-wise XOR operation is applied to the data read from Flash before passing to the BCH decoder. The scrambling works on the ECC sector boundaries.
Follow the rules listed below:
- Scrambler can be used when ECC is enabled or disabled.
- Scrambling must be enabled during write and read operations over the same page, otherwise data will be corrupted.
- Scrambler should not be used when the erased-page detection module is enabled.
In CDMA or PIO working mode, the scrambler_en bit in ecc_config_0 (0x0428) register enables this feature. For generic work mode, the scrambler can be enabled directly through the data sequence command.