Visible to Intel only — GUID: kjc1673393582714
Ixiasoft
Visible to Intel only — GUID: kjc1673393582714
Ixiasoft
5.1.6.13. Resets
When a cold or warm reset is issued to the HPS, the reset manager resets the EMAC module and holds it in reset until software releases it.
After the MPU boots up, it can deassert the reset signal by clearing the respective tsn* bit in the per0modrst register of the reset manager. Before deasserting the reset signal, you must configure the PHY interface type and all other corresponding EMAC settings in the system manager.
The following table shows the EMAC reset signals.
Reset | Input/Output | Description |
---|---|---|
rst_clk_app_n_o | Output | EMAC Application clock reset output to the FPGA fabric. This signal is generated synchronous to the application clock domain (aclk_i) during software reset |
emac_rst_clk_tx_n_o | Output | Transmit clock reset output to the FPGA fabric, which is the internal synchronized reset to phy_txclk_o output from the EMAC. It is generated synchronous to the clk_tx_i clock during software reset. May be used by logic implemented in the FPGA fabric as desired. The reset pulse width of the rst_clk_tx_n_o signal is three transmit clock cycles. |
emac_rst_clk_rx_n_o | Output | Receive clock reset output to the FPGA fabric, generated synchronous to the clk_rx_i during software reset. The reset pulse width of the rst_clk_rx_n_o signal is three transmit clock cycles. |