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Visible to Intel only — GUID: gpt1698276226202
Ixiasoft
A.4. Operational Status of the HPS to the FPGA Logic
This appendix describes how you can use the h2f_gp_out[31:0] signals to signal the operational status of the HPS to the FPGA logic.
- The h2f_gp_out[31:0] signals provide a low-latency, low-performance, and simple way to drive general-purpose signals to the fabric. One example is to use these signals to release specific FPGA logic from reset at certain stages of HPS operation.
The following table shows the features of all the signals described in this appendix.
Signal Name | Active High/Low | Source/Destination | Description |
---|---|---|---|
h2f_user0_clock | — | HPS-to-FPGA | General purpose interface clock to FPGA |
h2f_user1_clock | — | HPS-to-FPGA | General purpose interface clock to FPGA |
h2f_gp_out[31:0] | High = user defined as HPS ready Low = user defined as HPS not ready |
HPS-to-FPGA | General purpose interface signal to FPGA
Note: These signals go LOW during HPS resets and during SDM gating of HPS signals.
|
h2f_reset | High | HPS-to-FPGA | Indicates that the HPS is in warm reset, cold reset or Watchdog reset |
h2f_cold_reset | High | HPS-to-FPGA | Indicates that the HPS is in cold reset |
h2f_watchdog_rst | High | HPS-to-FPGA | Indicates that a Watchdog reset was triggered |
h2f_warm_reset_handshake_n (*_reset_req_n, *_reset_ack_n) |
|
|
Handshaking mechanism between the HPS and the FPGA during an HPS warm reset that is NOT triggered by a Watchdog timeout. |
nINIT_DONE | Low | SDM-to-FPGA | Use the nINIT_DONE output of the Reset Release Intel FPGA IP to hold your FPGA application logic in the reset state until the entire FPGA fabric is in user mode. |
- h2f_reset
- h2f_cold_reset
- h2f_warm_reset_handshake_n
- h2f_watchdog_reset