Visible to Intel only — GUID: tbx1665678616405
Ixiasoft
Visible to Intel only — GUID: tbx1665678616405
Ixiasoft
5.9. I2C Controller
The hard processor system (HPS) provides five I2C controllers to enable system software to communicate serially with I2C buses. Each I2C controller can operate in master or slave mode and support standard mode of up to 100 Kbps or fast mode of up to 400 Kbps. These I2C controllers are instances of the Synopsys™ DesignWare™ APB I2C (DW_apb_i2c) controller.
Each I2C controller must be programmed to operate in either master or slave mode only. Operating as a master and slave simultaneously is not supported.
Section Content
I2C Controller Differences Among Intel SoC Device Families
I2C Controller Use Cases
I2C Controller Features
I2C Controller System Integration
I2C Controller Signal Description
I2C Controller Functional Description
I2C Controller Programming Model
I2C Controller Address Map and Register Definitions
I2C Controller Design Guidelines and Examples