Visible to Intel only — GUID: faq1675983224624
Ixiasoft
Visible to Intel only — GUID: faq1675983224624
Ixiasoft
5.4.7.3.2. Command Queueing Error Recovery
The figure below shows an example command queueing error recovery procedure required to get the host controller and a device recovered from error state and prepare for following operations.
- The SD host controller always replies to the halt request by setting halt acknowledge. Software needs to wait for acknowledgement before running generic operation error recovery. The acknowledge is signaled after an unpredictable amount of time – the time required to finish any pending operation. The acknowledge is set when command and data paths report their status (whether they successfully completed or were interrupted by an error).
- The discard/task clear is required for the task interrupted by an error.
The command queueing reuses the protection mechanisms built into the SD host controller. It also adds an automatic error detection for the R1 device response.
Following is a full list of errors that can be detected by the command queueing:
- R1 response error
- Command errors (Index/CRC/End Bit/Timeout)
- Data transfer errors (CRC/End Bit/Timeout)
- DMA error
- Manager interface error
Once any of these errors is detected, the internal logic stops, reports the error type, and waits for the command queueing error recovery procedure.
Command queueing can send CMD13 SQS (Send Queue Status) to a device during the data transaction. If this feature is enabled (that is, CQRS16.CQSSCBC > 0) and a data transaction is in progress, the controller sends CMD13 SQS concurrently to the data transaction and reports possible CMD13 SQS error in the auto command error status registers (SRS15[4:1]).
SD/eMMC host controller might report current limit error but this error is command queueing task agnostic and will not interrupt transactions. This error is application-specific and, therefore, should be classified as a non-recoverable error. Software reaction must be adequate and follow the application assumptions.
SD/eMMC host controller does not use the response error check mechanism when command queueing is enabled.
Software can either poll the status registers or rely on the interrupts generated by the host controller. If an error occurs, it must raise a system interrupt, software enables the required interrupt status registers before task submission. The interrupt generation is configured by the following registers:
- Error Status Enable (SRS13[31:16])
- Error Signal Enable (SRS14[31:16])
- AXI Error Response (HRS03[19:16], HRS03[11:8])
- Response Error Detected Status Enable (CQRS05[2])
- Response Error Detected Signal Enable (CQRS06[2])
The following table describes the command queueing error cases.
Operation | Event | Consequence |
---|---|---|
Read task descriptor before CMD44 (task queueing) | Master error | Halt and report task ID in response mode error |
Read task descriptor before CMD46 / CMD47 (task execution) | Master error | Halt and report task ID in data transfer error |
Read task descriptor before DCMD (task execution) | Master error | Halt and report task ID in response mode error |
CMD44 | Command error | Halt and report task ID in response mode error |
CMD45 | Command error | Halt and report task ID in response mode error |
CMD13 while controller in idle | Command error | Halt and task ID is not reported |
CMD13 during CQ transaction | Command error | Halt and task ID is not reported |
CMD46 / CMD47 | Command error Data error DMA error |
Halt and report ID in data transfer error |
DCMD | Command error | Halt and report task ID in response mode error |
DCMD | Data timeout error | Halt and report task ID in response mode error |
Data transfer error in task error information is:
- set to 1 when error appears during CMD46 or CMD47
- clear to 0 when error appears during CMD44, CMD45, or DCMD
Response mode error in task error information is:
- set to 1 when error appears during CMD44, CMD45, or DCMD
- clear to 0 when error appears during CMD46 or CMD47
Task error information does not change when CQ is disabled or halted.