Visible to Intel only — GUID: qcu1673374141883
Ixiasoft
Visible to Intel only — GUID: qcu1673374141883
Ixiasoft
5.5.5. Combo DLL PHY Signal Description
Combo PHY Signal Name | Source Component | Description |
---|---|---|
dfi_ctrl_sel[0] |
System manager |
Selects whether the NAND or SD/eMMC DFI interface is active on the combo PHY pins. 0: NAND controller is active DFI interface 1: SD/eMMC is active DFI interface |
hpnfc_opr_mode[1:0] |
NAND Flash controller |
Mode of operation: 00 - Asynchronous mode 01 - ONFI 2.x synchronous mode NVDDR 10 - Toggle Mode 11 - other modes SD/eMMC Mode switching should be done while dll_rst_n is low. |
hpnfc_param_extended_rd |
NAND Flash controller |
Information to the PHY to keep RE# extended for a few controller clock cycles to guarantee data capture. This is applicable only to the SDR/Toggle Mode |
hpnfc_param_extended_wr |
NAND Flash controller |
Informs the PHY that the WE# can follow the WE# from the controller and that the controller takes care of the timing associated with the data and WE#. |
sd_param_extended_rd |
SD/eMMC host controller |
Information to the PHY to keep RE# extended for a few controller clock cycles to guarantee data capture. |
sd_param_extended_wr |
SD/eMMC host controller |
Informs the PHY that the WE# can follow the WE# from the controller and that the controller takes care of the timing associated with the data and WE#. |
clk_phy |
Clock manager |
Main clock used by the combo PHY |
clk_ctrl |
Clock manager |
Main clock used by NAND memory controller and SD/eMMC controller. |
hpnfc_dfi_init_complete sd_dfi_init_complete |
Combo PHY |
PHY initialization complete signals. These signals indicate that the PHY is initialized and ready to accept Flash memory device commands from the controller. The hpnfc signal is consumed by the NAND controller and the sd signal is consumed by the SD/eMMC controller |
hpnfc_dll_rst_n |
NAND Flash controller |
Resets the FIFO pointers in the read path. After deassertion, the primary DLL begins searching for lock. |
sd_dll_rst_n |
SD/eMMC host controller |
Resets the FIFO pointers in the read path. After deassertion, the primary DLL begins searching for lock. |
The following table shows the signals at the external interface with the NAND Flash device that are generated or consumed by the PHY module.
Signal Name | Description | Direction (PHY Perspective) | ASYNC ONFI1 (SDR) | ONFI2SYNC (NV-DDR) | TOGGLE |
---|---|---|---|---|---|
NAND_CE_N(CE#) | Chip enable | Out | Active low signal |
Active low signal |
Active low signal |
NAND_CLE(CLE) | Command latch enable | Out | Active high signal 1 during command cycle phase, else 0. |
Active high signal 1 during command cycle and data transfer phase, else 0. |
Active high signal 1 during command cycle phase, else 0. |
NAND_ALE(ALE) | Address latch enable | Out | Active high signal. 1 during address cycle phase, else 0. |
Active high signal. 1 during address cycle and data transfer phase, else 0. |
Active high signal. 1 during address cycle phase, else 0. |
NAND_RE_N (RE#) |
Read enable |
Out |
Falling edge of RE# activates read from the Flash device. Default value is 1. |
W/R# (Write/Read# Direction). For writes, value is 1 and for reads, value is 0. |
Rising edge of RE# activates read from the Flash device. Default value is 1. |
NAND_WE_N (WE#) | Write enable | Out | Data latched at rising edge of WE# by Flash device. The default value is 1. |
clk_phy (clk_phy is sent to Flash device). |
Data latched at rising edge of WE# by Flash device. The default value is 1. |
NAND_WP_N (WP#) | Write protect | Out | Active low signal | Active low signal | Active low signal |
NAND_DQS (DQS) | Data strobe | Bidirectional | Not Used Default value is 1. |
DQS = 1 during command and address phase. During data phase, DQS acts as normal DDR data strobe. |
DQS = 1 during command and address phase. During data phase, DQS acts as normal DDR data strobe. |
NAND_ADQ[15:0] (DQ[15:0]) | Data inputs/ outputs |
Bidirectional | Data bus | Data bus | Data bus |
NAND_RB_N (R/B#) | Ready /Busy#. One single device supported. | In | 0 => Device is busy. 1 => Device is not busy. |
0 => Device is busy. 1 => Device is not busy. |
0 => Device is busy. 1 => Device is not busy. |
The following table shows the signals at the external interface with the SD/eMMC Flash device that are generated or consumed by the PHY module.
Signal Name | Description | Direction (PHY perspective) |
---|---|---|
SDMMC_CLK (CLK) | SD/eMMC PHY to card clock signal | Out |
SDMMC_CMD (CMD) | Command/Response signal | Bidirectional |
SDMMC_DATA[7:0] (DATA[7:0]) | Data signal - data | Bidirectional |
SDMMC_DATA_STROBE | Data strobe signal | In |
SDMMC_PWR_ENA(BUS_POWER) | Device bus power | Out |
SDMMC_WRITE_PROTECT (WRITE_PROTECT) | Write protect input signal | In |
SDMMC_PU_PD_DATA2 (PU_PD_DATA2) | Pull-up/Pull-down signal for bit 2 of the DATA | Out |