Visible to Intel only — GUID: sru1675817054261
Ixiasoft
Visible to Intel only — GUID: sru1675817054261
Ixiasoft
5.4.6.4. Clocks
The following table describes the input clocks used by the SD/eMMC host controller and combo PHY when used in the SD/eMMC mode.
Clock | Description |
---|---|
s_pclk | This clock input is supplied from the APB clock. |
clk | This clock input is supplied from the AXI interface clock. |
sdphy_reg_pclk | Clock utilized by the APB interface that connects the host controller APB requester and combo PHY APB completer. |
sdmclk | This is the SD functional clock. It supplies the card interface unit/logic in the SD and eMMC mode. |
All the above clocks are sourced from the l4_mp_clk coming from the clock manager. The allowed l4_mp_clk clock frequency range is 50..200 MHz. You can gate all the clocks to the SD/eMMC host controller through the clock manager by using the perpllgrp.en.sdmmcclken register bitfield.
The following figure shows more details about the clocking of the SD/eMMC host controller and combo PHY.
The dfi_ctrl_sel[0] signal coming from system manager selects between enabling NAND and SD/eMMC as they are mutually exclusive and they share the same combo PHY. When SD/eMMC is enabled, the SD/eMMMC sdmclk clock and combo PHY clk_phy, and clk_ctrl clocks all have the same value. The l4_mp_clk is typically 200 MHz, and with the available 1/2/4 divider, so this clock can have the 200/100/50 MHz value. The SD card clock is obtained by dividing this clock by either 1 or a multiple of 2. Typical values for the clock are shown in the table below.
Device Type | Transfer Mode | Transfer Speed | Controller Frequency |
---|---|---|---|
SD | SDR12 | 12.5 MB/s | 50 MHz 23 |
SDR25 | 25 MB/s | 50 MHz | |
SDR50 | 50 MB/s | 100 MHz | |
SDR104 | 100 MB/s 24 | 200MHz | |
DDR50 | 50 MB/s | 50 MHz | |
eMMC | Legacy | 25 MB/s | 50 MHz23 |
High-speed SDR | 50 MB/s | 50 MHz | |
High-speed DDR | 100 MB/s | 100 MHz | |
HS200 (SDR) | 200 MB/s | 200 MHz | |
HS400 (DDR) | 400 MB/s | 200 MHz |
More information:
- Refer to Clock Manager chapter for more information about clocking.
- Refer to Combo DLL PHY chapter for more details about the Combo PHY operation.