Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.8.6.5.15. BUS RESET Generation DMA Controller Interface

To prevent a malfunctioning device from locking up the I3C/sideband bus, I3C protocol and JEDEC Sideband Specifications defines a bus protocol RESET mechanism.

The master controller supports the generation of following two patterns:

  • Timed reset
  • HDR-EXIT pattern

The reset pattern is selected in the RESET_CONTROL.BUS_RESET_TYPE field and to request the command is required to be written to 1b1 to RESET_CONTROL.BUS_RESET register field. The I3C controller considers this request only when it is in IDLE state and gives priority over scheduled regular commands. The master controller generates the timed reset by driving SCL Low and SDA low for SCL_LOW_MST_TIMEOUT[SCL_LOW_MST_TIMEOUT_COUNT] period of time. Once the controller completes the timed reset, the controller auto-clears the RESET_CONTROL.BUS_RESET request bit. The software can poll this request bit to know whether the controller completes the generation of the requested reset pattern, an interrupt is generated representing that the request reset pattern is issued.

Figure 190. SCL Timed Reset
Figure 191. HDR Exit Reset Pattern