LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813929
Date 4/08/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 LVDS SERDES Overview 2. Agilex™ 5 LVDS SERDES Architecture 3. Agilex™ 5 LVDS SERDES Transmitter 4. Agilex™ 5 LVDS SERDES Receiver 5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide 6. Agilex™ 5 LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Agilex™ 5 LVDS SERDES Design Guidelines 9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines 10. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Agilex™ 5 LVDS SERDES Architecture x
2.1. Agilex™ 5 HSIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Agilex™ 5 LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
4. Agilex™ 5 LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings for Non-DPA Mode
4.2.1. Receiver Input Clock Parameters Settings for Non-DPA Mode x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Planning the LVDS SERDES Interface 5.1.5. Generating the LVDS SERDES Intel® FPGA IP 5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.7. LVDS SERDES Intel® FPGA IP Signals
5.1.5. Generating the LVDS SERDES Intel® FPGA IP x
5.1.5.1. Intel® FPGA IP Generation Output
5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings 5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.6.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings x
5.1.6.2.1. HSIO Pin Index Number and Respective Channel Pin Selection 5.1.6.2.2. Placing Channel Bytes in I/O Lanes 5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Agilex™ 5 LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Agilex™ 5 LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL 8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
8.3. Pin Placement for Differential Channels x
8.3.1. I/O PLLs Driving LVDS SERDES Transmitter and Receiver Channels 8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank

If you use true differential I/O standards and single-ended I/O standards in the same or adjacent HSIO banks, adhere to the following placement guidelines.
  • Do not place true differential and toggling single-ended I/O standards in the combinations of locations listed in the following tables.
  • The Quartus® Prime software issues the following errors:
    • Compilation error—violation of the same bank placement restriction.
    • Critical warning—assignment of true differential I/O standards to pin pairs with the following pin index numbers: 0 and 1, 6 and 7, 88 and 89, and 94 and 95.
Table 36.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in the Same HSIO Bank

This table lists the combinations of pins and I/O standards not allowed in the same HSIO bank. Examples:

  • If you place a true differential I/O standard in pin pair 10 and 11, do not place single-ended I/O standards in pins 8 or 19.
  • If you place a single-ended I/O standard in pin 57 or 67, do not place a true differential I/O standard in pin pair 58 and 59.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin True Differential Pin Pair Single-Ended Pin
0 and 1 3, 4 24 and 25 27, 28 48 and 49 51, 52 72 and 73 75, 76
2 and 3 0 26 and 27 16, 24 50 and 51 40, 48 74 and 75 64, 72
4 and 5 1, 15 28 and 29 25, 39 52 and 53 49, 63 76 and 77 73, 87
6 and 7 9 30 and 31 22, 32 54 and 55 46, 56 78 and 79 70, 80
8 and 9 6, 11 32 and 33 31, 34 56 and 57 55, 58 80 and 81 79, 82
10 and 11 8, 19 34 and 35 33, 43 58 and 59 57, 67 82 and 83 81, 90
12 and 13 14, 17 36 and 37 38, 41 60 and 61 62, 65 84 and 85 86, 89
14 and 15 5, 12 38 and 39 29, 36 62 and 63 53, 60 86 and 87 77, 84
16 and 17 13, 26 40 and 41 37, 50 64 and 65 61, 74 88 and 89 85
18 and 19 10, 21 42 and 43 35, 45 66 and 67 59, 69 90 and 91 83, 92
20 and 21 18, 23 44 and 45 42, 47 68 and 69 66, 71 92 and 93 91, 94
22 and 23 20, 30 46 and 47 44, 54 70 and 71 68, 78 94 and 95 93
Table 37.  Restricted Pin Placement Combinations for True Differential and Single-Ended I/O Standards in Adjacent HSIO Banks

This table lists the combinations of pins and I/O standards not allowed in adjacent HSIO banks. Examples:

  • If you place a true differential I/O standard in pin pair 6 and 7 of bank 3B, do not place single-ended I/O standards in pin 95 of bank 3A.
  • If you place a single-ended I/O standard in pin 2 of bank 2B, do not place a true differential I/O standard in pin pair 88 and 89 of bank 2A.
Combinations Not Allowed (Pin Index Number) Combinations Not Allowed (Pin Index Number)
True Differential Single-Ended True Differential Single-Ended
Bank Pin Pair Bank Pin Bank Pin Pair Bank Pin
3A 88 and 89 3B 2 2A 88 and 89 2B 2
94 and 95 7 94 and 95 7
3B 2 and 3 3A 88 2B 2 and 3 2A 88
6 and 7 95 6 and 7 95

Refer to the related information for the figure showing the locations of the HSIO banks.

Related Information
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