5.1.7. LVDS SERDES Intel® FPGA IP Signals

LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

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Date 4/08/2024

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5.1.7. LVDS SERDES Intel® FPGA IP Signals

Table 21. Common LVDS SERDES IP TX and RX Signals
Signal Name	Width	Direction	Type	Description
`inclock`	1	Input	Clock	PLL reference clock.
`pll_areset`	1	Input	Reset	Active-high asynchronous reset to all blocks in LVDS SERDES IP and PLL. Note: This signal must always be connected to the reset logic.
`pll_locked`	1	Output	Control	Asserts when internal PLL locks.

Table 22. LVDS SERDES IP RX SignalsIn this table, `N` represents the LVDS SERDES interface width and the number of serial channels while `J` represents the SERDES factor of the interface.
Signal Name	Width	Direction	Type	Description
`rx_in_p` `rx_in_n`	`N`	Input	Data	LVDS serial input data differential pair.
`rx_bitslip_reset`	`N`	Input	Reset	Asynchronous, active-high reset to the clock-data alignment circuitry (bit slip).
`rx_bitslip_ctrl`	`N`	Input	Control	Positive-edge triggered increment for bit slip circuitry. Each assertion adds one bit of latency to the received bit stream.
`rx_dpa_hold`	`N`	Input	Control	Asynchronous, active-high signal that prevents the DPA circuitry from switching to a new clock phase on the target channel. Held high—selected channels hold their current phase setting. Held low—the DPA block on selected channels monitors the phase of the incoming data stream continuously and selects a new clock phase when needed. Applicable in DPA-FIFO mode only.
`rx_dpa_reset`	`N`	Input	Reset	Asynchronous, active-high reset to DPA blocks. Minimum pulse width: one parallel clock period. Applicable in DPA-FIFO and soft-CDR modes only.
`rx_fifo_reset`	`N`	Input	Reset	Asynchronous, active-high reset to FIFO block. Minimum pulse width: one parallel clock period. Applicable in DPA-FIFO mode only.
`rx_out`	`N×J`	Output	Data	Receiver parallel data output. DPA-FIFO and non-DPA modes—synchronous to `coreclock`. Soft-CDR mode—each channel has parallel data synchronous to its `rx_divfwdclk`.
`rx_bitslip_max`	`N`	Output	Control	Bit slip rollover signal. High when the next assertion of `rx_bitslip_ctrl` resets the serial bit latency to `0`.
`coreclock`	1	Output	Clock	Core clock for RX interfaces provided by the LVDS SERDES Intel® FPGA IP. Applicable in Non-DPA and DPA-FIFO modes only.
`rx_divfwdclk`	`N`	Output	Clock	The per channel and divided clock with the ideal DPA phase. This is the recovered slow clock for a given channel. Applicable in soft-CDR mode only. The `rx_divfwdclk` signals may not be edge-aligned with each other because each channel may have a different ideal sampling phase. Each `rx_divfwdclk` must drive the core logic with data from the same channel.
`rx_dpa_locked`	`N`	Output	Control	Asserted when the DPA block selects the ideal phase. Driven by the LVDS SERDES IP. Asserts when the signal settles on an ideal phase for that given channel. Deasserts when the DPA moves two phases in the same direction. Applicable in DPA-FIFO and soft-CDR modes only. Ignore all toggling of the `rx_dpa_locked` signal after `rx_dpa_hold` asserts.

Table 23. LVDS SERDES IP TX SignalsIn this table, `N` represents the LVDS SERDES interface width and the number of serial channels while `J` represents the SERDES factor of the interface.
Signal Name	Width	Direction	Type	Description
`tx_in`	`N×J`	Input	Data	Parallel data from the core.
`tx_out_p` `tx_out_n`	`N`	Output	Data	Serial output data differential pair.
`coreclock`	1	Output	Clock	Drives the core logic feeding the serializer.

Table 24. External PLL Signals for LVDS SERDES IPFor instructions on setting the frequencies, duty cycles, and phase shifts of the required PLL clocks for external PLL mode, refer to the Clock Resource Summary tab in the IP parameter editor.
Signal Name	Width	Direction	Type	Description
`ext_outclock_periph[1:0]`	2	Input	Clock	Fast clock. Used for serial data transfer. Required in all modes. Connect both ports to the IOPLL Intel® FPGA IP `lvds_clk[1:0]` ports. For more information about connecting this port with the signal from the IOPLL Intel® FPGA IP, refer to the related information.
`ext_pll_1_outclock2`	1	Input	Clock	Input clock to the LVDS SERDES Intel FPGA IP. Required for RX soft-CDR mode.
`ext_phout[7:0]`	8	Input	Clock	Provides the VCO clocks to the DPA circuitry for optimal phase selection. Required for all functional modes For more information about connecting this port with the signal from the IOPLL IP core, refer to the related information.
`ext_phout_periph`	1	Input	Clock	Input for the single VCO clock routed throughout the periphery. For more information about connecting this port with the `phout_periph` signal from the IOPLL IP core, refer to the related information.
`ext_pll_locked`	1	Input	Data	PLL lock signal. This signal indicates when external PLL is locked. It does not indicate if SERDES is ready for initialization.