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Ixiasoft
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
Visible to Intel only — GUID: yuz1688594269065
Ixiasoft
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
Document Version | Quartus® Prime Version | Changes |
---|---|---|
2024.08.23 | 2.14 | Made the following change:
|
2024.04.01 | 24.1 | Initial release. |