Hard Processor System Booting User Guide: Agilex™ 5 SoCs
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4.8. Configuration via Protocol
In the Configuration via Protocol (CvP) case, a small QSPI flash image is configured first, which brings up the PCIe* interface quickly. Then, later, the PCIe* host computer configures the fabric with the Core RBF file.
The following steps are involved:
- Compile hardware project with Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled file.
- Use Programming File Generator to create the following files:
- Peripheral JIC File: contains the initial configuration bitstream (including peripheral configuration data and SDM firmware) and a small SDM helper firmware image used by the Quartus® Prime Programmer to write the bitstream to flash.
- [Optional] Peripheral RPD File: contains the same initial configuration bitstream as the Peripheral JIC file, in simple binary format. Can be written to flash with a 3rd party programmer, such as U-Boot.
- Core RBF File: contains the FPGA configuration data, to be used by PCIe* host software later to configure the fabric. The HPS FSBL is included in the Core RBF file.
- [Optional] Map File: describes the actual flash usage in human-readable text format.
- The FPGA device is configured from the initial peripheral bitstream from QSPI flash, which brings up the PCIe* interface.
- The PCIe* host later configures the core fabric over PCIe* . This includes downloading and running HPS FSBL.