Hard Processor System Booting User Guide: Agilex™ 5 SoCs

ID 813762
Date 8/23/2024
Public
Document Table of Contents

5.3. ATF Zephyr* Boot

The following figure shows the overview of the HPS Boot Flow using the ATF as HPS bootloader to boot to Zephyr* RTOS.

Figure 36. The ATF Zephyr* Boot Flow
The boot flow is described in the following steps:
  1. The Configuration Management Firmware (CMF) running on the SDM loads the FSBL, which is ATF BL2, into HPS On-Chip RAM and then bring the HPS boot core out from reset.
  2. The ATF BL2 loads the SSBL and OS, which is ATF BL31 and Zephyr* RTOS, into DDR.
  3. The ATF BL2 jumps to ATF BL31.
  4. The ATF BL31 sets up the GIC, EL3 environment, and initializes the PSCI services.
  5. The ATF BL31 jumps to the Zephyr* RTOS.
Note: The Zephyr* RTOS can access the SDM FPGA features through ATF BL31 through the Arm* Secure Monitor Call (SMC) and Mailbox.

For information on Exception Levels, refer to Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.