Hard Processor System Booting User Guide: Agilex™ 5 SoCs

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ID 813762
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. HPS Boot Flows 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 5 SoC FPGA Boot Flow 8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
1. Introduction x
1.1. Glossary 1.2. Agilex™ 5 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 3.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options 4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. HPS Boot Flows x
5.1. U-Boot ATF Linux* Boot 5.2. ATF Linux Boot 5.3. ATF Zephyr* Boot
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux* 6.3. FPGA Partial Reconfiguration from Linux*
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA) Edition
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs

2.1. Boot Flow Overview for FPGA Configuration First Mode

You can program the Agilex™ 5 SoC device to configure the FPGA first and then boot the HPS. The available configuration data sources configure the FPGA core and periphery first in this mode. After completion, you may optionally boot the HPS. All of the I/Os, including the HPS-allocated I/O, are configured and brought out of tri-state. If the HPS is not booted:

  • The HPS is held in reset.
  • HPS-dedicated I/O are held in reset.
  • HPS-allocated I/O are driven with reset values from the HPS.

If the FPGA is configured before the HPS boots, the boot flow looks like the example figure below. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).

Figure 1. Typical FPGA Configuration First Boot Flow
Table 2.  FPGA Configuration First StagesThe sections following this table describe each stage in more detail.
Time Boot Stage Device State

TPOR to T1

POR

Power-on reset

T1 to T2

Secure Device Manager (SDM)-Boot ROM
  1. SDM samples the MSEL pins to determine the configuration scheme and boot source.
  2. SDM establishes the device security level based on eFuse values.
  3. SDM initializes the device by reading the configuration firmware (initial part of the bitstream) from the boot source.
  4. SDM authenticates and decrypts the configuration firmware (this process occurs as necessary throughout the configuration).
  5. SDM starts executing the configuration firmware.

T2 to T3

SDM-configuration firmware
  1. SDM I/O are enabled.
  2. SDM configures the FPGA I/O and core (full configuration) and enables the rest of your configured SDM I/O.
  3. SDM loads the FSBL from the bitstream into HPS on-chip RAM.
  4. HPS boot core start executing FSBL code.
  5. SDM enables HPS SDRAM I/O and optionally enables HPS debug.
  6. FPGA is in user mode.
  7. HPS is released from reset. All non-boot cores are in a wait-for-interrupt (WFI) state.

T3 to T4

First-Stage Bootloader (FSBL)
  1. HPS verifies the FPGA is in user mode.
  2. The FSBL initializes the HPS, including the SDRAM.
  3. HPS loads SSBL into SDRAM.
  4. HPS peripheral I/O pin mux and buffers are configured. Clocks, resets, and bridges are also configured.
  5. HPS I/O peripherals are available.

T4 to T5

Second-Stage Bootloader (SSBL)
  1. HPS bootstrap completes.
  2. OS is loaded into SDRAM.

T5 to TBoot_Complete

Operating System (OS)

The OS boots and applications are scheduled for runtime launch.

Section Content
Power-On Reset (POR)
Secure Device Manager
First-Stage Bootloader
Second-Stage Bootloader
Operating System
Application

Level Two Title