Visible to Intel only — GUID: zcu1689662028173
Ixiasoft
1.2.1.1.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.1.2.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.1.1.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP
1.2.1.1.2.5. Connect Interfaces and Signals
1.2.1.1.2.6. Clear System Warnings and Errors
1.2.1.1.2.7. Configuring the Reset Vector of the Nios® V Processor
1.2.1.1.2.8. Saving and Generating System HDL
1.2.1.2.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.2.2.2. Adding On-Chip Memory (RAM or ROM) Intel® FPGA IP
1.2.1.2.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.2.2.4. Adding System ID Peripheral Intel® FPGA IP
1.2.1.2.2.5. Adding Reset Release Intel FPGA IP
1.2.1.2.2.6. Connect Interfaces and Signals
1.2.1.2.2.7. Clear System Warnings and Errors
1.2.1.2.2.8. Saving and Generating System HDL
Visible to Intel only — GUID: zcu1689662028173
Ixiasoft
1.2.1.1.2.8. Saving and Generating System HDL
- Save the system.
- Click Generate HDL at the bottom right corner of the Platform Designer.
- Leave all settings at default, and click Generate.
- Ensure that the Nios® V processor hardware system is successfully generated.
Figure 19. Successful Generation
- The Platform Designer generates a folder named niosv_top, which stores the system generation files.
- Exit the Platform Designer, and return to the project front page.
Figure 20. Generated Project Files