AN 985: Nios® V Processor Tutorial

ID 784468
Date 7/24/2024
Public
Document Table of Contents

1.2.1.1.2.5. Connect Interfaces and Signals

Connect the clock bridge, reset bridge, reset release IP, and Nios® V processor to the peripherals.
Table 1.  Connection between Host and Agent
IP Host Peripheral
Clock Bridge IP out_clk intel_niosv_m_0.clk
intel_onchip_memory_0.clk1
jtag_uart_0.clk
Reset Bridge IP out_reset intel_niosv_m_0.reset
intel_onchip_memory_0.reset1
jtag_uart_0.reset
Reset Release IP ninit_done intel_niosv_m_0.reset
intel_onchip_memory_0.reset1
jtag_uart_0.reset
Nios® V/m Processor IP platform_irq_rx jtag_uart_0.irq
instruction_manager intel_onchip_memory_0.s1
data_manager intel_onchip_memory_0.s1
jtag_uart_0.avalon_jtag_slave
Figure 16. Full System Connection