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Ixiasoft
1.2.1.1.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.1.2.2. Adding On-Chip Memory II (RAM or ROM) Intel® FPGA IP
1.2.1.1.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP
1.2.1.1.2.5. Connect Interfaces and Signals
1.2.1.1.2.6. Clear System Warnings and Errors
1.2.1.1.2.7. Configuring the Reset Vector of the Nios® V Processor
1.2.1.1.2.8. Saving and Generating System HDL
1.2.1.2.2.1. Adding Nios® V/m Processor Intel® FPGA IP
1.2.1.2.2.2. Adding On-Chip Memory (RAM or ROM) Intel® FPGA IP
1.2.1.2.2.3. Adding JTAG UART Intel® FPGA IP
1.2.1.2.2.4. Adding System ID Peripheral Intel® FPGA IP
1.2.1.2.2.5. Adding Reset Release Intel FPGA IP
1.2.1.2.2.6. Connect Interfaces and Signals
1.2.1.2.2.7. Clear System Warnings and Errors
1.2.1.2.2.8. Saving and Generating System HDL
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1.2.2.1. Creating a Platform Designer System
- Click New, select Platform Designer System File, and click OK.
Figure 9. New Window
- In the Open System window, check the project information.
- Quartus project: <Working directory>/niosv_top.qpf
- Revision: niosv_top
- Device family: Agilex 7
- Device part: AGFB014R24B2E2V
- Platform Designer system: Click Create new Platform Designer System icon, and name the QSYS file as niosv_top.
Figure 10. Open System Window - Click Create.
- In the Platform Designer system, the software instantiates the Clock Bridge and Reset Bridge Intel® FPGA IP by default.
- In Clock Bridge IP, configure Explicit clock rate as 100000000 Hz (100 MHz).
- In Reset Bridge IP, enable it as an Active low reset.
Figure 11. Default Platform Designer System
Section Content
Adding Nios V/m Processor Intel FPGA IP
Adding On-Chip Memory II (RAM or ROM) Intel FPGA IP
Adding JTAG UART Intel FPGA IP
Adding Reset Release Intel FPGA IP
Connect Interfaces and Signals
Clear System Warnings and Errors
Configuring the Reset Vector of the Nios V Processor
Saving and Generating System HDL