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1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet FPGA IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
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2.5.2. Design Constraints
The following is the current constraint statements in the project .qsf file:
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE ED8401
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
You must replace the constraint statements in the project .qsf file if you are using the following version of the Agilex™ 7 I-Series Transceiver SoC development kit:
Serial Number ID | Constraint Statements Required in the Project .qsf | Action Required |
---|---|---|
2000001 | set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888 set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12" |
Replace the current constraints in the QSF file with these constraints. |
Refer to Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide for more information on the Agilex™ 7 I-Series Transceiver-SoC development kit and their respective serial number identifier.
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