Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab Status Control PMA Setting Data Type Error Control Run Control 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

4.2.5.1. The QSFPDD NRZ Tab

Figure 11. The QSFPDD-01 NRZ Tab
Figure 12. The QSFPDD-23 NRZ Tab

The following sections describe controls in the QSFPDD NRZ tab.

Status

The Status control displays the following status information during the loopback test:
  • PLL Lock: Shows the PLL locked or unlocked state.
  • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence is detected.
  • Detail: Shows the PLL lock and pattern sync status of each channel. The number of the error bits of each channel can be found here.
Figure 13. QSFPDD NRZ—PLL and Pattern Status

Control

Use the following controls to select an interface to apply PMA settings, data type, and error control:
  • QSFPDD0 x8
  • QSFPDD1 x8
  • QSFPDD2 x8
  • QSFPDD3 x8

PMA Setting

The PMA Setting control allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:

  • Serial Loopback: Displays the signal status between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
    • Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.
Figure 14. QSFPDD NRZ-PMA Setting

Data Type

The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:
  • PRBS7: Pseudo-random 7-bit binary sequences
  • PRBS15: Pseudo-random 15-bit binary sequences
  • PRBS23: Pseudo-random 23-bit binary sequences
  • PRBS31: Pseudo-random 31-bit binary sequences (default)

Error Control

This control displays data errors detected during analysis and allows you to insert errors:

  • Detected Errors: Displays the number of data errors detected in the received bit stream.
  • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Bit Error Rate: Calculates the bit error rate of the transmit data stream.
  • Insert: Insert a one-word error into the transmit data stream each time you click the button. Insert is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.

Run Control

  • TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions can achieve.
  • Start: This control initiates the loopback tests.
  • Data Rate: Displays the XCVR type and data rate of each channel.
Figure 15. QSFPDD NRZ—Data Rate
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