Intel Agilex® 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

Download PDF
ID 776646
Date 5/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configure the FPGA Device by Avalon® -ST (AvST) Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.5. General Input/Output

Table 9.   Intel® MAX® 10 and FPGA
Schematic Signal Name Description
F_GPIO0 The value of filtered user_pb[0]​
F_GPIO1 The value of filtered user_pb[1]​
F_GPIO2 Reserved​
F_GPIO3 Reserved​
F_GPIO4 Reserved​
F_GPIO5 Reserved​
F_GPIO6 Reserved​
F_GPIO7 ​Reserved
F_GPIO8 ​Reserved
F_GPIO9 ​Reserved
F_GPIO10 ​Used for DIP Switch
F_GPIO11 ​Used for Switch Data Transfer
Table 10.  System Intel® MAX® 10
Schematic Signal Name Description
USER_PB0 User Push Button
USER_PB1 User Push Button
USER_SW0 User Switch
USER_SW1 User Switch
USER_SW2 User Switch
USER_SW3 User Switch
USER_SW4 User Switch
USER_SW5 User Switch
USER_SW6 User Switch
USER_SW7 User Switch
SYS_PWR_RSV3 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV2 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV1 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV0 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
USER_LED0 User LED
USER_LED1 User LED
USER_LED2 User LED
USER_LED3 User LED
USER_LED4 User LED
USER_LED5 User LED
USER_LED6 User LED
USER_LED7 User LED
F_GPIO0 The value of filtered user_pb[0]​
F_GPIO1 The value of filtered user_pb[1]​
F_GPIO2 MCIO_PERST in RP Mode​
F_GPIO3 FMC_A_PERST in RP Mode​
F_GPIO4 FMC_B_PERST in RP Mode​
F_GPIO5 Reserved​
F_GPIO6 ​Reserved
F_GPIO7 ​Reserved
F_GPIO8 ​Reserved
F_GPIO9 ​Reserved
F_GPIO10 ​Reserved
F_GPIO11 ​Reserved
SYS_SW0​

Factory load:

0—Load image from Page 0 of the QSPI
SYS_SW1​ NU ​
SYS_SW2​ ​NU
SYS_SW3​ ​NU
SYS_SW4​ ​NU
SYS_SW5​

FMC-A PCIe RP/EP Select:​

"0": RP​

"1": EP​
SYS_SW6​

FMC-B PCIe RP/EP Select:​

"0": RP​

"1": EP​
SYS_SW7​

MCIO PCIe RP/EP Select:​

"0": RP​

"1": EP​
SYS_LED0/D9​ PGM_LED0 for Avalon® -ST (AVST) configuration​
SYS_LED2/D11​ PGM_LED1 for AVST configuration​
SYS_LED4/D13​ PGM_LED2 for AVST configuration​
SYS_LED6/D15​ MAX_ERROR for AVST configuration​
SYS_LED1/D10​ MAX_LOAD for AVST configuration​
SYS_LED3/D12​ MAX_CONF_DONE for AVST configuration​
SYS_LED5/D14​ Reserved​
SYS_LED7/D16​ Reserved​
SYS_PB0/S11​ MAX_RESETn​
SYS_PB1/S12​ FPGA_RESETn​
SYS_PB2/S14​ Power recycle​
SYS_PB3/S16​ PGM_SEL for AVST configuration​
SYS_PB4/S17​ PGM_CFG for AVST configuration​
FPGA_FAN_PWM FAN 2 PWM SIGNAL
FPGA_FAN_TACH FAN 2 TACHOMETER SIGNAL
QSFP_RIGHT_FAN_PWM FAN 3 PWM SIGNAL
QSFP_RIGHT_FAN_TACH FAN 3 TACHOMETER SIGNAL
QSFP_LEFT_FAN_PWM FAN 1 PWM SIGNAL
QSFP_LEFT_FAN_TACH FAN 1 TACHOMETER SIGNAL
CORE_FETS_FAN_PWM FAN 0 PWM SIGNAL
CORE_FETS_FAN_TACH FAN 0 TACHOMETER SIGNAL
MUX_SEL0 MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_12A_8_DP/N (OR) REFCLK_FGT_12A_9_DP/N FOR FMCA_RECRD_CLK 0: FMCA_RECRD_CLK= REFCLK_FGT_12A_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_12A_9_DP/N
MUX_SEL1 MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_13C_8_DP/N (OR) REFCLK_FGT_13C_9_DP/N FOR FMCB_RECRD_CLK 0: FMCA_RECRD_CLK= REFCLK_FGT_13C_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_13C_9_DP/N
MCIO_CLK_SEL_EP_N TIED TO MUX_DIP_SW2
MCIO_CLK_ENN TIED TO MUX_DIP_SW3
MUX_DIP_SW0 DIP SWITCH 0 SIGNAL (by default high)—tie this to MUX_SEL0
MUX_DIP_SW1 DIP SWITCH 1 SIGNAL (by default high)—tie this to MUX_SEL1
MUX_DIP_SW2 MCIO_CLK_SEL_EP_NN:

LOW BEFORE SYSTEM POK

HIGH AFTER SYSTEM POK
MUX_DIP_SW3 MCIO_CLK_ENN:

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
VCCL_I2C_EN CONNECT VCCL_SCL/SDA TO SYSTEM Intel® MAX® 10 (DEFAULT ENABLE-1)
R_13C_PERST_IO_N DRIVEN LOW
R_13B_PERST_IO_N TIED TO MCIO PREST INTERNALLY
R_12B_PERST_IO_N DRIVEN LOW
R_12C_PERST_IO_N DRIVEN LOW
SI5395_1_A_IN_SEL0_R DNU
SI5395_2_A_OEN_SYS_R

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
SI52204_PWRGD_R TIED TO SYSTEM POWER OK
SI5395_2_A_IN_SEL0_R DNU
SI5395_1_A_OEN_SYS_R

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
SI5391_A_OEN

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
SI5391_A_RSTN

LOW UNTIL SYSTEM POK

HIGH AFTER SYSTEM POK
SI5518_GPIO_0_R DNU
CLK_OE_0_N

SI52204 CLK ENABLE0:

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
CLK_OE_1_N

SI52204 CLK ENABLE1:

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
CLK_OE_2_N

SI52204 CLK ENABLE2:

HIGH BEFORE SYSTEM POK

LOW AFTER SYSTEM POK
SI5518_GPIO_1_R DNU
SI5518_GPIO_2_R DNU
CLK_SI5395_2_FINC_R DNU
CLK_SI5395_2_FDEC_R DNU
CLK_SI5395_1_FINC_R DNU
CLK_SI5395_1_FDEC_R DNU
SI5518_I2C_R_EN

KEEP IT ENABLE:

LOW BEFORE SYSTEM POK

DNU AFTER POK
R_12A_SPARE_N DRIVEN LOW
R_13A_SPARE_N DRIVEN LOW
DIMM_IO_R_EN

ENABLE ALWAYS AFTER SYSTEM POK

LOW BEFORE SYSTEM POK

DNU AFTER SYSTEM POK
FMC_B_PCIE_PERSTN_3V3 DNU
FMC_B_PCIE_WAKEN_3V3 DNU
FMC_A_PCIE_WAKEN_3V3 DNU
FMC_A_PCIE_PERSTN_3V3 DNU
Table 11.  UB2/PWR Intel® MAX® 10
Schematic Signal Name Description
FPGA_POK_LED FPGA Power Good
SYS_PWR_RSV0 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV1 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV2 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
SYS_PWR_RSV3 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
PWR_PB0 POWER MAX PB0—FU
Level Two Title