Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

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ID 776646
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. BTS Functionalities 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. BTS Functionalities x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configuring the FPGA Device by Avalon® Streaming Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.4. Clocks

Table 8.  Default Clock Frequency
Schematic Signal Name Default Frequency (Hz)
125M_F_OSC_CLK1 125M
CLK_TOD_10M_DN/DP 10M
CLK_1PPS_1V2_FM91 1
DDR_1_166.66M_REFCLK_DN/DP 166.66M
DDR_2_166.66M_REFCLK_DN/DP 166.66M
DDR_3_166.66M_REFCLK_DN/DP 166.66M
DDR_4_166.66M_REFCLK_DN/P 166.66M
CLK_100M_GPIO_2C_DN/DP 100M
1PPS_SMA_OUT_1V2 1
CLK_100M_GPIO_4_DN/DP 100M
CLK_PCIE_EP_MCIO1_DP/DN 100M
CLK_PCIE_RP_MCIO1_DP/DN 100M
PCIE_100M_REF_AP/AN 100M
SYS_M10_50M 50M
PWR_M10_50M 50M
SMA_1PPS_OUT 1
SMA_10MHZ_OUT 10M
REFCLK_FGT_12A_8_DP/DP Not assigned
REFCLK_FGT_12A_9_DP/DP Not assigned
FMCA_RECRD_CLK_DP/DN Not assigned
REFCLK_FGT_13C_8_DP/DN Not assigned
REFCLK_FGT_13C_9_DP/DN Not assigned
FMCB_RECRD_CLK_DP/DN Not assigned
OCXO_19.44MHZ 19.44M
SI5518_REF_IN_R 54M
SI5518_XTAL_XA 54M
FMCA_ETH_REFCLK_156.25M_DP/DN 156.25M
FMCB_ETH_REFCLK_156.25M_DP/DN 156.25M
SI5518_OUT2_1PPS_PLL_FB 1
FMCA_CPRI_REFCLK_153.6M_DP/DN 153.6M
FMCB_CPRI_REFCLK_153.6M_DP/DN 153.6M
FMCA_CPRI_REFCLK_184.32M_DP/DN 184.32M
FMCB_CPRI_REFCLK_184.32M_DP/DN 184.32M
CLK_TOD_10M_DP/DN 156.25M
CLK_1PPS_FM91 1
CLK_1PPS_OUT_SMA 1
CLK_10M_OUT_SMA 10M
CLK_SI5518_FREQ_OUT12_156.25M_DP/DN 156.25M
CLK_SI5518_FREQ_OUT14_156.25M_DP/DN 156.25M
REFCLK2_PCIE_100M_DP/DN 100M
REFCLK1_PCIE_100M_DP/N 100M
SI52204_CLKIN 25M
SI5391_XA 48M
CLK_FHT_13B_156.25M_DP/DN 156.25M
CLK_FHT_13C_156.25M_DP/DN 156.25M
CLK_FGT_13B_156.25M_DP/DN 156.25M
CLK_FGT_13B_156.25M_SPARE_DP/DN 156.25M
CLK_FGT_13A_156.25M_DP/DN 156.25M
CLK_FGT_13A_156.25M_SPARE_DP/DN 156.25M
CLK_SI5395_1_OUT9A_DP/DN 100M
CLKGEN_SI5395_2_XA 48M
CLK_FHT_12B_156.25M_DP/DN 156.25M
CLK_FHT_12C_156.25M_DP/DN 156.25M
CLK_FGT_12C_156.25M_DP/DN 156.25M
CLK_FGT_12C_156.25M_SPARE_DP/DN 156.25M
CLK_FGT_12B_156.25M_DP/DN 156.25M
CLK_FGT_12B_156.25M_SPARE_DP/DN 156.25M
CLK_SI5395_2_OUT9A_DP/DN 100M
FX2_XTALIN 24M
Figure 33. Clock Tree
Level Two Title