Intel Agilex® 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide

Download PDF
ID 776646
Date 5/31/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore Board QSPI Flash with the Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The FMCA NRZ Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD400 PAM4 Tab 4.2.5.5. The QSFP NRZ Tab 4.2.5.6. The SFP Tab 4.2.5.7. The OSFP Tab
5. Development Kit Hardware and Configuration x
5.1. Configure the FPGA Device by Active Serial (AS) Modes (Default Mode) 5.2. Configure the FPGA Device by Avalon® -ST (AvST) Modes
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Communication Interfaces A.8. Daughter Cards
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

3.1. Default Settings

The Intel Agilex® 7 FPGA I-Series Transceiver Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.

Note: X refers to Don't Care in the table below.
Table 3.  Factory Default Switch Settings
Switch Default Position Default Function
S19 [1:4] ON / OFF/ ON / ON System MAX-10 selected I JTAG Chain
S20 [1:4] ON / ON / ON / ON Mode 1: On-board Intel download circuit act as the only JTAG Master.
S9[1:4] ON / OFF / OFF / X

Agilex FPGA Mode Select pins.

Default JTAG
S10 [1:4] ON / ON / ON / ON

SYS_SW[0:3]

SYS_SW[0]–-> Factory Loadn

‘0’ – Load image from Page 0 of the QSPI

S15 [1:4] ON / ON / ON / OFF

SYS_SW[4:7]

SYS_SW[4]-->X

SYS_SW[5]–->

FMC-A PCIe RP/EP Select

“0”: RP (Default)

“1”: EP

SYS_SW[6]–->

FMC-B PCIex RP/EP Select

“0”: RP (Default)

“1”: EP

SYS_SW[7]–->

Not used

“0”: RP

“1”: EP (Default)

S1[1:4]

S6 [1:4]

OFF /OFF / OFF / OFF

OFF / OFF/ OFF / OFF

User Switch [0:3]

User Switch [4:7]

S22[1:4]

ON / ON / ON / ON

MUX_DIP_SW[0:3]

Mapped as below:

MUX_DIP_SW0 --> MUX_SEL0

MUX_DIP_SW1 --> MUX_SEL1

MUX_DIP_SW2 --> MCIO_CLK_SEL_EP_N; RP

MUX_DIP_SW3 --> MCIO_CLK_ENN
S7 OFF Board power supply
S4 ON / ON / ON / ON Future Development
Level Two Title